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E2U0027-28-83
Semiconductor MSM7540L/7560L
Semiconductor Single Rail ADPCM CODEC
This version: Aug. 1998 MSM7540L/7560L Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7540L/7560L are single channel ADPCM CODEC ICs which perform mutual transcoding between an analog voice band signal 300 to 3400 Hz and 32 kbps ADPCM serial data. Using advanced circuit technology, these devices operate from a single 3 V power supply and provide low power consumption. The MSM7540L/7560L are optimized for advanced digital cordless telephone system applications.
FEATURES
* Single 3 V Power Supply Operation * ADPCM Algorithm : Complies completely with 1988's version ITU-T G.721 (32 kbps)
* Transmit/Receive Full-Duplex Operation * Transmit/Receive Synchronous Mode Only 32 kbps to 2048 kbps * Serial ADPCM Transmission Data Rate : 64 kbps to 2048 kbps * Serial PCM Transmission Data Rate : * PCM Interface Coding Format MSM7540L : A-law or Linear (14 bit, 2's compliment) Selectable MSM7560L : m-law or Linear (14 bit, 2's compliment) Selectable * Low Power Consumption Operating Mode : 18 mW Typ. (VDD = 3.0 V) Power-Down Mode : 0.3 mW Typ. (VDD = 3.0 V) Externally Adjustable Gain * Two Analog Input Amplifier Stages : Push-pull Drive (direct drive of 350 W + 120 nF) * Analog Output Stage : * Built-in Crystal Oscillator (10.368 MHz) * Built-in Reference Voltage Supply * Option Reset Specified by ITU-T G. 721/ADPCM * Package: 28-pin plastic SOP (SOP28-P-430-1.27-K) (Product name: MSM7540LGS-K) (Product name: MSM7560LGS-K) 32-pin plastic TSOP (TSOPI32-P-814-0.50-1K) (Product name: MSM7560LTS-K)
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BLOCK DIAGRAM
Semiconductor
V DD AG DG AIN1 GSX1 AIN2 GSX2 SG PDN MCK RES LPS AOUT+ -1
- + - +
X1
X2
- +
RCLPF
A/D Conv.
0 BPF 1
COMPANDER
1 0
ADPCM CODER 0 1
P / S P / S S / P S / P
XSYNC IS BCLKA
V REF
PCMSO
CLOCK/ TIMING
PCMSI BCLKB PCMRI
1 0 1 LPF 0 0 1
AOUT- PWI VFRO
P / S
PCMRO
RCLPF
D/A Conv.
EXPANDER
ADPCM DECODER
S / P
IR RSYNC
MSM7540L/7560L
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Semiconductor
MSM7540L/7560L
PIN CONFIGURATION (TOP VIEW)
RES 1 PCMRI 2 PCMRO 3 IR 4 IS 5 PCMSI 6 PCMSO 7 LPS 8 DG 9 AG 10 SG 11 AIN1 12 GSX1 13 AIN2 14 28 BCLKB 27 BCLKA 26 XSYNC 25 RSYNC 24 MCK 23 X2 22 X1 21 PDN 20 VDD 19 AOUT+ 18 AOUT- 17 PWI 16 VFRO 15 GSX2
28-Pin Plastic SOP
X1 X2 NC MCK RSYNC XSYNC BCLKA BCLKB RES PCMRI PCMRO IR IS NC PCMSI PCMSO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
PDN VDD NC AOUT+ AOUT- PWI VFRO GSX2 AIN2 GSX1 AIN1 SG AG NC DG LPS
NC: No connection 32-Pin Plastic TSOP
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Semiconductor
MSM7540L/7560L
PIN AND FUNCTIONAL DESCRIPTIONS
AIN1, AIN2, GSX1, GSX2 Transmits analog input and the output for transmit gain adjustment. AIN1 (AIN2) connects to the inverting input of the internal transmit amplifier. GSX1 (GSX2) connects to the output of the internal transmit amplifier output. Refer to Fig. 1 for gain adjustment. VFRO, AOUT+, AOUT-, PWI Receives analog output and the output for receive gain adjustment. VFRO is receive filter output. AOUT+ and AOUT- are differential analog signal outputs which can directly drive ZL = 350 W + 120 nF. Refer to Fig. 1 for gain adjustment.
Analog Input
C1
R1
AIN1
- +
R2 GSX1 C2 R3 AIN2
- +
to ENCODER
R4 GSX2 Transmit Gain: = (R2/R1) (R4/R3) RS* Receive Gain: = (R6/R5) R5 PWI VFRO from DECODER
R6 AOUT- - +
Z L =120 nF + 350 W
V0
Analog Output
-1 AOUT+ *: Side Tone Pass (Gain = R6/RS)
Figure1 Analog Input/Output Interface 4/15
Semiconductor SG
MSM7540L/7560L
Analog signal ground voltage output. The output voltage of this pin is approximately 1.4 V. Put bypass capacitors between this pin and the AG pin. During power-down this output voltage is 0 V. The external SG voltage, if necessary, should be used via a buffer. AG Analog ground. DG Digital ground. This ground is separated internally from the analog signal ground pin (AG). The DG pin must be kept as close as possible to AG on the PCB. VDD +3 V power supply. LPS PCM coding law selection. MSM7540L only; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the A-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value character signal (2's complement). MSM7560L only; if this pin goes to a "0" level, PCMSO, PCMSI, PCMRO, and PCMRI become the m-law character signal, and if these pins goes to a "1" level, the signal becomes a linear value character signal (2's complement). PDN Power down control input. If this pin is "0", this device is in the power-down state. Normally, this pin is set to "1". RES Optional reset input specified by ITU-T Recommendation G. 721. If this pin is "0", the device is in the reset state. The reset width (during "L") should be 125 ms or more. MCK Master clock input. The frequency must be 10.368 MHz. The master clock signal may be asynchronous to BCLKA, BCLKB, XSYNC, and RSYNC. PCMSO Transmit PCM data output. PCM is output from MSB in synchronization with the rising edge of BCLKB and XSYNC.
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Semiconductor PCMSI
MSM7540L/7560L
Transmit PCM data input. This signal is converted to transmit ADPCM data. PCM is shifted in synchronization with the falling edge of BCLKB. Normally, this pin is connected to PCMSO. PCMRO Receive PCM data output. PCM is the output signal after ADPCM decoder processing. This signal is output serially from MSB in synchronization with the rising edge of BCLKB and RSYNC. PCMRI Receive PCM data input. PCM is shifted on the falling edge of the BCLKB input from MSB. Normally, this pin is connected to PCMRO. IS Transmit ADPCM signal output. After having encoded PCM with ADPCM, this signal is output from MSB in synchronization with the rising edge of BCLKA and XSYNC. This pin is an open drain output and remains in a high impedance state during power-down. IS requires a pull-up resistor. IR Receive ADPCM signal input. The ADPCM signal is shifted in series and synchronization with the falling edge of BCLKA and RSYNC and output from MSB. BCLKB Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI). The frequency is set in the 64 kHz to 2048 kHz range. XSYNC 8 kHz synchronous signal input for transmit PCM and ADPCM data. Synchronize this signal with BCLKA and BCLKB signal. XSYNC is used to indicate the MSB of the serial PCM and ADPCM data stream. Be sure to input the XSYNC signal because it is also used as the imput of the timing generator. RSYNC 8 kHz synchronous signal input for receive PCM and ADPCM data. Synchronize this signal with BCLKA and BCLKB signal. RSYNC is used to indicate the MSB of the serial PCM and ADPCM data stream. BCLKA Shift clock input for the ADPCM data (IS, IR). The frequency is set in the of 32 kHz to 2048 kHz range.
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Semiconductor X1, X2
MSM7540L/7560L
Crystal oscillator (10.368 MHz) connection. Connect X2, the clock output pin, directly to the MCK pin. When using a conventional external clock of 10.368 MHz, X1 should be connected to the ground, X2 open, and provide the external clock through the MCK pin.
MSM7540L/60L X1 X2 MCK MSM7540L/60L X1 X2 MCK
10.368 MHz
10.368 MHz
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Semiconductor
MSM7540L/7560L
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition -- -- -- -- Rating -0.3 to +5 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -55 to +150 Unit V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Input High Voltage Symbol VDD Ta VIH Condition Voltage must be fixed -- MCK, XSYNC, RSYNC, PCMRI, PCMSI, BCLKA, BCLKB, IR, LPS, PDN, RES MCK, XSYNC, RSYNC, PCMRI, Input Low Voltage Master Clock Frequency Bit Clock Freqency Synchronous Signal Frequency Clock Duty Ratio Digital Input Rise Time VIL fMCK fBCKA fBCKB fSYMC DC tIr PCMSI, BCLKA, BCLKB, IR, LPS, PDN, RES MCK BCLKA BCLKB XSYNC, RSYNC MCK, BCLKA, BCLKB MCK, XSYNC, RSYNC, PCMRI, PCMSI, BCLKA, BCLKB, IR, LPS, PDN, RES MCK, XSYNC, RSYNC, PCMRI, Digital Input Fall Time tIf tXS tXS tRS tSR tWS tDS tDH RDL CDL CSG PCMSI, BCLKA, BCLKB, IR, LPS, PDN, RES Transmit Sync Signal Setting Time Receive Sync Signal Setting Time Synchronous Signal Width PCM, ADPCM Set-up Time PCM, ADPCM Hold Time Digital Output Load Bypass Capacitor for SG BCLKA, BCLKB to XSYNC XSYNC to BCLKA, BCLKB BCLKA, BCLKB to RSYNC RSYNC to BCLKA, BCLKB XSYNC, RSYNC -- -- IS (Pull-up Resistor) IS, PCMSO, PCMRO SGGND 100 100 100 100 1 BCLK 100 100 500 -- -- -- -- -- -- -- -- -- -- -- 10+0.1 -- -- -- -- 100 -- -- -- 100 -- ns ns ns ns ms ns ns W pF mF -- -- 50 ns -- -- 50 ns -0.01% 32 64 -- 30 10.368 -- -- 8.0 50 0 -- Min. 2.7 -25 0.45 VDD Typ. -- +25 -- Max. 3.6 +75 VDD Unit V C V
0.16 VDD +0.01% 2048 2048 -- 70
V MHz kHz kHz kHz %
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Semiconductor
MSM7540L/7560L
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
Parameter Power Supply Current Input High Voltage Input Low Voltage Input Leakage Current Output Low Voltage Output Leakage Current Input Capacitance Symbol IDD1 IDD2 VIH VIL IIH IIL VOL IO CIN VI = VDD VI = 0 V 1 LSTTL, Pull-up: 500 W IS -- Condition Operating Mode, No Signal (VDD = 3.0 V) Power Down Mode (VDD = 3.0 V) -- -- (VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Min. -- -- 0.45 VDD 0.0 -- -- 0.0 -- -- Typ. 6 0.1 -- -- -- -- 0.2 -- 5 Max. 12 0.2 VDD 0.16 VDD 2.0 0.5 0.4 10 -- Unit mA mA V V mA mA V mA pF
Transmit Analog Interface Characteristics
Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Input Offset Voltage SG Output Voltage SG Output Inpedance SG Rise Time Symbol RINX RLGX CLGX VOGX VOFGX VSG RSG TSG Condition AIN1, AIN2 GSX1, GSX2 GSX1, GSX2 GSX1, GSX2, RL = 20 kW Pre-OPAMPs -- -- GNDSG 10 mF + 0.1 mF (Rise Time to 90% of max. level) -- 700 -- ms Min. 10 20 -- -- -20 -- -- Typ. -- -- -- -- -- 1.4 40 Max. -- -- 100 *1.300 +20 -- 80 Unit MW kW pF VPP mV V kW
Receive Analog Interface Characteristics
Parameter Input Resistance Output Load Resistance Output Capacitance Symbol RINPW PWI RLVF RLAO CLVF CLAO VOVF Output Voltage Level VOAO VOFVF Offset Voltage VOFAO GDB VFRO AOUT+, AOUT- VFRO AOUT+, AOUT- VFRO, AOUT+, AOUT- VFRO AOUT+, AOUT- (GAIN = 0 dB), Power amp only Power amp (0.3 to 3.4 kHz, ZL = 350 W + 120 nF)(See Fig.1) RL = 50 kW RL = 1.2 kW ZL = 350 W + 120 nF(See Fig.1) Condition Min. 10 50 1.2 -- -- -- -- -- -100 -20 40 Typ. -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- 100 100 *1.300 *1.300 *1.300 +100 +20 -- Unit MW kW kW pF pF VPP VPP VPP mV mV dB
Open Loop Gain
*
-7.7 dBm (600 W) = 0 dBm0, + 3.14 dBm0 = 1.300 VPP (MSM7540L) -7.7 dBm (600 W) = 0 dBm0, + 3.17 dBm0 = 1.300 VPP (MSM7560L)
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Semiconductor AC Chracteristics
Condition Parameter Symbol LOSS T1 Transmit Frequency Response LOSS T3 LOSS T4 LOSS T5 LOSS T6 LOSS R1 Receive Frequency Response LOSS R2 LOSS R3 LOSS R4 LOSS R5 SD T1 Transmit Signal to Distortion Ratio SD T2 SD T3 SD T4 SD T5 SD R1 Receive Signal to Distortion Ratio SD R2 SD R3 SD R4 SD R5 GT T1 Transmit Gain Tracking GT T2 GT T3 GT T4 GT T5 GT R1 Receive Gain Tracking GT R2 GT R3 GT R4 GT R5 1020 1020 1020 1020 Freq. (Hz) 0 to 60 1020 3300 3400 3968.75 0 to 3000 1020 3300 3400 3968.75 3 0 -30 -40 -45 3 0 -30 -40 -45 3 -10 -40 -50 -55 3 -10 -40 -50 -55 -- -0.2 -0.5 -1.2 -- -0.2 -0.5 -1.2 -0.2 (*1) (*1) 0 -- -0.15 0 13 35 35 35 28 23 35 35 35 28 23 -0.2 LOSS T2 300 to 3000 0 -- Level (dBm0)
Others
MSM7540L/7560L
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Min. 25 -0.15 -0.15 0 13 -0.15 Typ. -- -- Reference -- -- -- -- Reference -- -- -- -- -- -- -- -- -- -- -- -- -- -- Reference -- -- -- -- Reference -- -- -- +0.2 +0.5 +1.2 +0.2 +0.5 +1.2 +0.2 +0.80 0.80 -- -- -- -- -- -- -- -- -- -- -- +0.2 +0.80 0.80 -- +0.20 Max. -- +0.20 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
*1 Use the P-message weighted filter
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Semiconductor AC Characteristics (Continued)
Condition Parameter Symbol Freq. (Hz) NIDLT Idle Channel Noise NIDLR AVT 1020 AVR PSRRT tSDX Digital Output Delay Time tSDR tXD1 tXD2 tXD3 -- 1 LSTTL + 100 pF, Pull-up: 500 W -- Noise Freq. Noise Level : 50 mVPP 0 VFRO -- 0.285 30 30 50 50 50 50 50 -- -- -- Level (dBm0) AIN = SG
Others
MSM7540L/7560L
(VDD = 2.7 V to 3.6 V, Ta = -25C to +70C) Min. Typ. Max. -68 (-75.7) -72 (-79.7) 0.359 0.359 -- -- 200 200 200 200 200 Vrms Vrms dB dB ns ns ns ns ns dBm0p (dBmp) Unit
(*1) (*1) (*2) GSX2
-- -- 0.285
-- -- 0.320 (*3) 0.320 (*3) -- -- -- -- -- -- --
Absolute Signal Amplitude Power Supply Noise Rejection Ratio
PSRRR : 0 to 50 kHz
*1 Use the P-message weighted filter *2 PCMRI input code "11010101"(MSM7540L) "11111111"(MSM7560L) *3 0.320 Vrms = 0 dBm0 = -7.7 dBm Note: All ADPCM coder and decoder characteristics comply with ITU-T Recommendation G.721.
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Semiconductor
MSM7540L/7560L
TIMING DIAGRAM
Transmit Side PCM/ADPCM Data Interface
BCLKB XSYNC PCMSO PCMSO (during linear)
0
txs
tsx
1
2
tws txd2
3
4
5
6
7
8
9
10
11
12
13
14
txd1
txd3
MSB
tsdx
LSB
txd3
MSB
LSB
BCLKA XSYNC IS
0
txs
tsx txd1 tsdx
1
2
txd2
3
4
5
txd3
6
7
8
9
10
MSB
LSB
Receive Side PCM/ADPCM Data Interface
BCLKA RSYNC
tds tdh txd3
0
trs
tsr
1
2
tws
3
4
5
6
7
8
9
10
11
12
13
14
IR
0
trs
MSB
LSB
BCLKB RSYNC
tsr
1
2
3
4
5
6
7
8
9
10
trd1
trd2
txd3
PCMRO
tsdx
MSB MSB
LSB
trd3
PCMRO (during linear)
LSB
Note: Linear format A code of an input/output level is determined by the 14-bit 2'compliment. Refer to the table below for code format.
Input/Output level +Full-scall 0 -Full-scall MSB to LSB 01111111111111 00000000000000 10000000000000
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Semiconductor
MSM7540L/7560L
APPLICATION CIRCUIT
V DD
MSM7540L/7560L
V DD 1 2 Receive PCM Output Receive ADPCM Input Transmit ADPCM Output 3 4 5 6 Transmit PCM Output 7 8 9 10 11 Transmit Analog Input 12 13 14 RES PCMRI PCMRO IR IS PCMSI PCMSO LPS DG AG SG AIN1 GSX1 AIN2 BCLKB BCLKA XSYNC RSYNC MCK X2 X1 PDN V DD AOUT+ AOUT- PWI VFRO GSX2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10.368 MHz
ADPCM Algorithm Reset Input Shift Clock Input for PCM, ADPCM Data (64 kHz to 2048 kHz) 8 kHz Sync Signal Input
Power Down Input
Receive Analog Output (Push-Pull)
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Semiconductor
MSM7540L/7560L
PACKAGE DIMENSIONS
(Unit : mm)
SOP28-P-430-1.27-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.75 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM7540L/7560L
(Unit : mm)
TSOPI32-P-814-0.50-1K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.27 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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